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analog delay line

  • 模拟延迟线

网络释义专业释义英英释义

  [电讯] 模拟延迟线

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analog charge delay line 模拟电荷延迟线

  • 模拟延迟线 - 引用次数：2

    Finally with CAD tool PSpice the emulation of analog delay line and some improvement of comparator is implemented. It is proved that the improvement scheme of back logic circuit is effective and can increase the system speed.

    仿真实验表明,本文提出的后逻辑支持电路改进方案可以提高测试系统速度;模拟延迟线定时分辨率较高,但是定时精度却难以提高,因此延迟线必须走集成化的道路。

    参考来源 - 集成电路测试系统后逻辑支持电路改进与模拟延迟线性能分析
  • 模拟延迟线

·2,447,543篇论文数据，部分数据来源于NoteExpress

Analog delay line

  • abstract: An analog delay line is a network of electrical components connected in series, where each individual element creates a time difference or phase change between its input signal and its output signal. It operates on analog signals whose amplitude varies continuously.

以上来源于: WordNet

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